Process technology trends in semiconductor manufacturing suggest that power dissipation is a major design challenge in high performance VLSI chips. For all circuit applications it is highly desirable to reduce and limit power dissipation in deep sub-micron semiconductor designs. In high performance server applications, for example, power dissipation leads to expensive packaging and cooling solutions. On the other end of the performance spectrum, the widespread use of battery operated devices, such as lap top computers, mobile phones and personal digital assistants (PDA's)—without significant advances in battery technology—creates an urgent need to address power dissipation in integrated circuits.
Consistent with constant electric field scaling, semiconductor power supply voltages have been reduced by thirty percent with each technology generation. The reduction in power supply voltage is necessary to manage active power dissipation as well as to maintain circuit reliability. With power supply voltage scaling, the device threshold voltage (Vt) must be reduced to maintain or improve performance. Depending on the process technology, this reduction in Vt leads to an exponential increase in sub-threshold leakage current, which, in some cases, may represent the primary source of power dissipation in the chip. Indeed, for current microprocessor designs, power dissipation due to sub-threshold leakage current constitutes 40-50 percent of total chip power. Consequently, a clear need exists to develop novel techniques for controlling and reducing leakage power, especially since leakage power is expected to grow by a factor of five with each new generation of process technology.
Techniques for the control and reduction of sub-threshold leakage current may be divided into two approaches: static and dynamic. The static approach to low-leakage circuit design is directed to circuit geometries rather than to a functional aspect of the circuit. Such circuit design techniques are intended to reduce leakage current regardless of the mode of chip operation. Dynamic techniques, on the other hand, allow the dynamic control of certain functional blocks of the design during functional operation. In this regard, dynamic techniques involve setting certain functional blocks of the chip into low-leakage mode when they are in “idle” or “sleep” state. Power gating is one common dynamic leakage control mechanism that involves turning off the power supply when the functional block is in idle state. This is achieved by connecting a transistor, referenced as the sleep transistor or power gating switch, in series with the power supply of the logic block. When the functional block is in sleep state, the sleep transistor is turned off, thereby reducing the power dissipated by the logic block. In practice, a network of power gating switches may be necessary to efficiently control and reduce leakage power dissipation.
Power gating techniques involve partitioning the chip into functional logic blocks that may be selectively powered up or down. Circuits that may be periodically powered down are isolated from the primary power distribution network by placing them in voltage islands. A voltage island represents a predefined block of circuitry incorporating an internal power distribution network that is isolated from the primary power distribution network of the integrated circuit.
The power gating switch is a large transistor providing connectivity between the primary power distribution network of the integrated circuit and the voltage island power distribution network. The number of power gating switches necessary to supply the electrical load of the voltage island is dependent on the physical area and capacitive loading of the active circuitry contained within the voltage island. The power gating switches enable the circuitry within the voltage island to be disconnected from the primary power distribution network to reduce the total power dissipation of the integrated circuit during periods when the voltage island circuitry is in idle state.
By turning on the power gating switch, the voltage island and the chip-level power distribution networks are connected and power is supplied to the circuits in the voltage island from the chip power grid through the power gating switches. Conversely, turning off the power gating switch disconnects the voltage island power grid from the chip power grid, thus reducing power dissipation since the circuits in the voltage island are disconnected from the power supply.
FIG. 1 shows a prior art schematic diagram of a voltage island with power gating switches connecting the voltage island power grid 101, 102 and the chip power distribution networks 103, 104. The power gating switches are modeled as PFET transistors and labeled as S0, S1, . . . , Sn in the schematic. As shown in the schematic in FIG. 1, the chip-level circuits 105 draw power from the chip VDD and GND power grids 103, 104 while the voltage island circuits 106 draw power from voltage island VDD and GND power grids 101, 102. Power supplied to the voltage island is controlled by the power gating switches 100.
Due to the significant physical area of typical a power gating switch, a large number of switches in a voltage island will consume a significant portion of the total voltage island area. Thus, it is desirable to minimize the number of switches in a voltage island. However, it is important to have enough switches to guarantee the electrical robustness of the voltage island power distribution. For instance, the power gating switch design specification dictates a maximum current limit, IPGS that can be supplied through the switch. Hence, a minimum of NPGS=IVI/IPGS switches are needed to supply a total current, IVI to the voltage island.